1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device having an error correction function.
2. Description of the Related Art
A synchronous semiconductor memory device synchronized with a clock has been used for high-speed data transfer. For example, a synchronous DRAM using a 3-stage-pipelined architecture has been disclosed as a synchronous semiconductor memory device (e.g., see Y. Takai et al, “250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture”, IEEE J. Solid-State Circuits, Vol. 29, No. 4, Apr. 1994).
Here, assume that an error correction function is applied to the synchronous semiconductor memory device as described above. FIG. 1 is a view showing only the configuration along data buses in a DRAM macro that the semiconductor memory device includes, to which an ECC (error checking and correction) has been applied.
A cell array CA and sense amplifier SA, a control circuit DQBUFBLK, and an ECC input/output block ECCIOBLK are arranged from the right in FIG. 1. 16 column selection lines CSL are input to the sense amplifier SA. A DQ buffer DQBUF and RD line drive circuit RDDRV are arranged on the control circuit DQBUFBLK. The DQ buffer DQBUF includes a DQ line read buffer and DQ line write buffer which perform a column redundancy control and DQ line control. The RD line drive circuit RDDRV drives an RD line.
Arranged on the ECC input/output block ECCIOBLK are circuit blocks including an input buffer DINBUF and output buffer DOUTBUF which perform data input/output controls, a code generation circuit CODEGEN for realizing an ECC function, a syndrome generator SYNDGEN, and an error correction circuit EC, and a WD line drive circuit WDDRV for driving a WD line. The code generation circuit CODEGEN generates a code at the data write time. The syndrome generator SYNDGEN generates a syndrome at the data read time. The error correction circuit EC decodes the syndrome and performs an error correction.
FIG. 2 is a view for explaining the data flow at the write operation time in FIG. 1. The external data bus width is set to 128 bits and input data DIN is transmitted, as 128-bit data WDx, through the input buffer DINBUF. The code generation circuit CODEGEN uses the 128-bit data WDx as information bit to generate an error correction code. A systematic hamming code that can correct a single-bit error and detect a double-bit error is used as the error correction code. At this time, it is sufficient for a check code to have a 9-bit length, so that the code length of the error correction code becomes 137 bits, which is obtained by adding 128 bits as information bit and 9 bits as parity bit. The coded 137-bit data WDy is driven in the WD line drive circuit WDDRV, transmitted to the DQ buffer DQBUF, and written in memory cells through the DQ line. The DQ line is a complementary signal line pair of DQt/DQc and includes four DQ line pairs for column redundancy.
FIG. 3 is a view for explaining the data flow at the read operation time in FIG. 1. The data including a column redundancy and parity bit for ECC is read out from the cell array, passed through a 141-bit DQ line, and input to the DQ buffer DQBUF. The data that has been input to the DQ buffer DQBUF is subjected to a redundancy control and transmitted to a 137-bit RD line. The data read out to the RD line is driven in the RD line drive circuit RDDRV to become data RDy and reaches the syndrome generator SYNDGEN in the ECC input/output block ECCIOBLK and error correction circuit EC.
Of the 137-bit data RDy, 9 bits as parity bit and 128 bits as information bit are input to the syndrome generator SYNDGEN. The syndrome generator SYNDGEN then generates a 9-bit syndrome. The generated syndrome is decoded in the error correction circuit EC. When any errors exist in the 128-bit information bit RDy, the error correction circuit EC corrects the error, if possible. The error-corrected information bit RDx is output to the outside as data DOUT through the data output buffer DOUTBUF.
At this time, the external data bus width has been set to 128 bits and information length used when a data coding process and data error correction are performed in the DRAM macro has also set to 128 bits. In this case, there is no big problem as to a pipeline operation, as described below.
FIGS. 4A and 4B are views each showing a pipeline operation at that time in a schematic manner. FIG. 4A shows a read operation and FIG. 4B shows a write operation.
In FIG. 4A, when column address CA0 is sequentially input in response to the input of read command <R>, read operation (R0) including an address decode, selection of the column selection lines CSL, and data read out to the RD line is performed in Cycle 0. In Cycle 1, read operation (R1) for column address CA1 is performed in the same manner as read operation (R0). At the same time, error correction operation (E0) is performed for the data read out by read operation (R0) for column address CA0. In Cycle 2, read operation (R2) for column address CA2, error correction operation (E1) for column address CA1 and output operation (Q0) for column address CA0 are performed in parallel.
In FIG. 4B, write command <W> and write data <D0> for column address CA0 are input and code generation operation (E0) is performed in Cycle 0. Subsequently, in Cycle 1, after write command <W> and write data <D1> for column address CA1 have been input, code generation operation (E1) and write operation (W0) for column address CA0 are performed. The operations in the subsequent cycles are performed in the same manner as described above.
However, in the above pipeline operations, when the external data bus width is smaller than the information length used at the error correction time, or the bit width of the data to be input becomes substantially smaller than the information length due to an application of a byte mask function, the following problem occurs.
In a semiconductor memory device having an error correction function, information bit is coded and stored in a plurality of memory cells at the write operation time; and when the data that has been read out from memory cells includes any errors, the data is subjected to an error correction and output to the outside at the read operation time. In general, the larger the information length, the smaller the percentage of the parity bit needed for an error correction becomes. This is effective when using an error correction code.
However, in a semiconductor memory device having a configuration in which there is a possibility that, when the external input bus width is smaller than the internal bus width or due to an application of a byte mask function, the length of the data to be written in memory cells becomes substantially smaller than information length (although the external input bus width is not necessarily smaller than the internal bus width), an operation called “Read-Modify-Write in ECC” is required. Therefore, speed penalty becomes noticeable to significantly degrade the performance. In the “Read-Modify-Write in ECC”, assuming that the internal bus width is substantially equal to the code length of an error correction code, data is once read out from memory cells by its code length and an error correction operation is applied to the data at the write operation time. After that, the data that has been read out and corrected is overwritten with externally input write data having a length smaller than the information length. Finally, the data is coded and written in memory cells.
FIG. 5 shows the data flow at the write operation time in this case. The information length of an error correction code is set to 128 bits and the code length thereof is set to 137 bits. An external input has a 16-bit bus width. The bus width inside a DRAM macro is, when including parity bit, 137 bits, which is substantially the same as the code length. The data to be input is only 16 bits, so that it is impossible to use 128-bit code, if nothing is done.
In this case, therefore, the following operation needs to be performed.
(1) Data is read out from memory cells at the corresponding address by 137 bits.
(2) An error correction is performed to obtain correct 128-bit information bit, and the correct 128-bit information bit is overwritten with the input 16-bit write data to be written. A code is generated for the overwritten new information bit to obtain data WDy with 137-bit code data to be written in memory cells.
(3) The code data WDy is written in memory cells.
FIGS. 6A, 6B, and 6C are views each showing an operation in the case where the bit width of the input data is smaller than the information length. The read operation shown in FIG. 6A is entirely the same as that shown in FIG. 4A.
The write (Read-Modify-Write) operation shown in FIG. 6B is performed as follows. When write command W is sequentially input as in the case of FIG. 4B, read operation (R0) is performed in Cycle 0, error correction and coding (E0) are performed in Cycle 1, and write operation (W0) is performed in Cycle 2. In read operation (R0), column selection lines CSL corresponding to address CA0 are selected and data is read out from memory cells. In write operation (W0), column selection lines CSL corresponding to address CA0 are selected and coded data is written in memory cells.
At this time, when write command W corresponding to address CA2 is input in Cycle 2, read operation (R2) is performed in Cycle 2. Therefore, read operation (R2) and write operation (W0) are performed simultaneously in Cycle 2. That is, column selection lines CSL corresponding to different addresses are activated at the same cycle in the sense amplifier SA shown in FIG. 1, which may bring about data collision. In order to prevent the data collision, the cycle time must be extended. For example, as in the case of the write operation shown in FIG. 6C, when read operation (R0), error correction coding (E0), and write operation (W0) are performed in one cycle, the data collision does not occur. In this case, however, the cycle time is obviously increased to make it impossible to perform high-speed data transfer.